This application claims priority to Korean Application No. 00-41427, filed Jul. 19, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to the field of integrated circuit fabrication in general and, more particularly, to the removal of anti-reflective layers during integrated circuit fabrication.
As the density of integrated circuits increase, so may the need for forming fine patterns therein. For example, integrated circuit memory devices with a capacity of 1-Gigabit or more may need a pattern size having a design rule of about 0.2 xcexcm or less. However, it may be difficult to use conventional i-line photoresists to form such fine patterns. Thus, a photolithography technique using Deep Ultraviolet (DUV) photoresist has been suggested.
It is known to deposit a photoresist layer on multiple material layers of an integrated circuit device and expose a portion of the photoresist layer to light develop the photoresist layer into photoresist patterns. An anti-reflective layer may be formed under the photoresist layer to prevent diffusion reflection from the underlying layers during exposure and thereby achieve higher resolution photolithography.
In particular, it is known to use a silicon oxynitride layer as the anti-reflective layer with a DUV photoresist. The silicon oxynitride layer can suppress diffusion reflection from the underlying layers. Furthermore, the silicon oxynitride layer may reduce undesirable effects that may occur during patterning of the photoresist layer. For example, the silicon oxynitride layer may help avoid a phenomenon referred to as photoresist poisoning, which can lead to a footing phenomenon after development of the photoresist layer.
FIGS. 1A through 1D are cross-sectional views that illustrate a conventional method for fabricating integrated circuits. In particular, FIGS. 1A through 1D illustrate a photolithography process in which a silicon oxynitride layer can be used as an anti-reflective film in forming a gate electrode of a transistor.
First, according to FIG. 1A, a doped polysilicon layer and an anti-reflective layer, such as a silicon oxynitride layer, are sequentially deposited on an integrated circuit substrate 10 having an isolation region 12 and an oxide layer. After forming a photoresist pattern 28 on the resultant structure, the anti-reflective layer, the doped polysilicon layer and the oxide layer are sequentially etched using the photoresist pattern 28 as an etching mask, thereby resulting in an anti-reflective pattern 26, a gate electrode 24 and a gate oxide layer 22 as shown in FIG. 1A.
Next, the photoresist pattern 28 is removed to expose the anti-reflective pattern 26 on the gate electrode 14, as shown in FIG. 1B. The exposed anti-reflective pattern 26 can have a thickness of about 300 to 400 Angstroms. According to some conventional techniques, the anti-reflective pattern 26 can be removed during a cleaning process that uses a mixture of NH4OH, H2O2 and deionized water in a ratio of 1:4:20 by volume (hereinafter, referred to as xe2x80x9cSC-1xe2x80x9d) as the cleaning solution. In other conventional processes an HF solution can be used as the cleaning solution. The cleaning process can be followed by a rinsing process using deionized water.
Unfortunately, when SC-1 is used to etch the anti-reflective pattern 26, the underlying polysilicon layer of the gate electrode 24 may also be etched. On the other hand, if an HF solution is used to remove the anti-reflective pattern 26, the anti-reflective pattern 26 may not be fully removed, such that a remnant anti-reflective pattern 26a may remain on the gate electrode 24. Moreover, the remnant anti-reflective pattern 26a may include semi-spherical defects (or seeds).
The defects can be caused by the porous nature of the silicon oxynitride layer. In particular, when an unstable porous structure, such as the silicon oxynitride layer, is present on a hydrophobic layer, such as the polysilicon layer, a portion of the unstable porous structure (i.e., the silicon oxynitride layer) may remain on the surface of hydrophobic layer (i.e., the polysilicon layer) after cleaning. Seeds may have an increased tendency to form on a hydrophobic layer compared to a hydrophilic layer, due to the presence of dangling bonds on its surface.
The remaining portion of the silicon oxynitride layer may react with silica (SixOy) in the deionized water that is used in the rinsing process to cause the semi-spherical defects. The remnant anti-reflective pattern 26a may act as a barrier in subsequent ion implantation or metal silicide formation, thereby increasing the probability of a device failure.
The remnant anti-reflective pattern 26a, including the semi-spherical defects which remains on the gate electrode 24, may be removed by increasing the amount of etching during the a chemical cleaning process. However, as shown in FIG. 1D, the isolation region 12 may be unacceptably recessed or an undercut 22a may be formed in the gate oxide layer 22 by increased etching. Thus, it can be difficult to provide processing margins sufficient to remove the anti-reflective pattern 26 while reducing over etching of other portions of the integrated circuit.
Embodiments according to the present invention can provide methods and compositions for the removal of anti-reflective layers during fabrication of integrated circuits. Pursuant to these embodiments, an anti-reflective pattern or layer can be removed from an integrated circuit using a solution that includes a fluorine containing compound, an oxidant, and water. In some embodiments, the fluorine containing compound in the solution is Hydrogen Fluoride (HF). Preferably, the oxidant in the solution is H2O2. In some embodiments, the oxidant in the solution is ozone water. The water can be deionized water.
In some embodiments according to the present invention, the solution can be about 50% or more oxidant by volume. In some embodiments according to the present invention, a ratio of the fluorine containing compound to the oxidant in the solution can be in a range between about 14:800 and 14:1000 by volume. In some embodiments according to the present invention, the fluorine containing compound can be an HF solution that is 49% pure.
In other embodiments according to the present invention, the oxidant can be 30% pure H2O2 that is in a range between about 50% and 80% of the solution by volume. In other embodiments according to the present invention, a ratio of the fluorine containing compound to the oxidant to the deionized water in the solution can be in a range between about 14:1100:300 to 14:1000:400 by volume.
In other embodiments according to the present invention, an integrated circuit can be fabricated by forming a conductive layer on an integrated circuit substrate. An anti-reflective layer can be formed on the conductive layer. A photoresist pattern can be formed on the anti-reflective layer. The anti-reflective layer and the conductive layer can be etched using the photoresist pattern as an etching mask to provide an anti-reflective pattern and a gate electrode. The anti-reflective pattern can be removed using a solution containing a fluorine containing compound and an oxidant.
In some embodiments according to the present invention, an anti-reflective layer removal composition can include a solution of a fluorine containing compound, an oxidant, and water. The solution can about 50% or more oxidant by volume. In some embodiments according to the present invention, a ratio of the fluorine containing compound to the oxidant in the solution can be in a range between about 14:800 and 14:1000 by volume. In other embodiments, the solution can be less than about 80% oxidant by volume. In some embodiments according to the present invention, the water can be deionized water.
In some embodiments according to the present invention, the conductive layer can be polysilicon. In some embodiments according to the present invention, the anti-reflective layer can be a silicon oxynitride layer. In some embodiments according to the present invention, the anti-reflective layer can be formed by one of a chemical vapor deposition and a physical vapor deposition.